Research Overview
Analog circuit netlists specify electrical connectivity, but they do not fully express the physical constraints and design intent needed for layout. Device matching, local environment, guard rings, well-domain relations, passive-device access, and routing geometry must still be handled explicitly during physical implementation.
This research investigates how selected analog layout techniques can be studied, organized, and translated into reusable concepts for analog layout automation.
Research Path
The work follows a manual-to-automatic sequence:
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Manual layout study
Selected layout techniques are examined using controlled layout variants of a two-stage operational amplifier. -
Technique–effect–metric framework
Each layout technique is related to its intended physical effect, suitable evaluation method, implementation trade-off, and automation implication. -
Automation-oriented representation
Generated analog modules preserve boundaries, placement footprints, terminals, routing access, guard-ring geometry, and well-domain information. -
Reusable module generation
Primitive and row-level generators are composed into current mirrors, differential pairs, Wilson mirrors, cascoded structures, and MIM capacitor modules. -
Analog-aware placement
Multistart B*-tree placement combines generic and circuit-aware initial configurations. -
Well-domain repair and hierarchical assembly
Post-placement repair handles n-well spacing and supports compact same-nwell domain connections. -
Access-aware top-level routing
Guard-ring, point-to-point, and multi-terminal connections are handled by separate routing policies.
Implementation Environment
The prototype was developed in an open-source SKY130/OpenPDKs environment using Magic, xschem, and ngspice.
Explore the Research
Manual Layout Study
Controlled-variable layout variants examine spacing, guard-ring isolation, and matching-oriented placement.
Conceptual Framework
Manual observations are organized by physical effect, evaluation metric, trade-off, and automation implication.
Automation-Oriented Representation
Module geometry and selected analog-aware metadata are preserved as explicit interfaces for placement, assembly, and routing.
Generator Architecture
Reusable device and row-level structures are composed into selected analog module families.
Analog-Aware Placement
Multistart B*-tree placement combines generic and analog-aware seed topologies with local search and post-placement n-well spacing repair.
Access-Aware Routing
Generated module interfaces are converted into effective endpoints, access-safe routing objects, separated net classes, and incremental top-level routing trees.
Full-Flow Case Study
Generated modules are placed, repaired for well-domain constraints, assembled hierarchically, and routed at top level.
Public Portfolio Scope
This website presents the research motivation, methodology, selected figures, summarized results, and technical documentation of the project.
The implementation source code and university project files, including raw circuit netlists and simulation code, are maintained separately and are not distributed through this public portfolio.